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Walsh
- 利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .
MIPS32Barrelshifter
- VHDL MIPS 32位桶形移位器的设计-VHDL MIPS 32-bit barrel shifter design
case4
- DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extens
f_divider
- 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
VHDL_32bit_timer
- VHDL写的32位计数，两个四位共阳数码管输出 串口输出+数码管显示的计时器程序 每次停止后串口输出。-VHDL to write 32-bit count, a total of two 4-yang control output serial digital output+ digital tube displays each stopped the timer program serial output.
Move071221133_32
- 用Verilog HDL语言或VHDL语言来编写，实现32位的桶形移位器。 并在Quartus Ⅱ上实现模拟仿真；-With the Verilog HDL language or VHDL language to write to achieve 32-bit barrel shifter. To achieve in the Quartus Ⅱ simulation
serialports2
- 使用verilog以及VHDL编写的将串口数据转换为32位并口数据，作为FPGA和DSP接口使用（DSP型号：6205）-Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
VEDA7LED
- 采用QUARTUS II 7.2 (32-BIT)工具实现的两位7段数码管动态扫描显示的VHDL程序。硬件电路采用8位拨位开关控制，高四位控制左数码管，第四位控制右数码管。芯片采用EP1C6T144FPGA器件。-By QUARTUS II 7.2 (32-BIT) tools to achieve the two 7-segment digital tube dynamic scan showed the VHDL program. 8-bit hardware with dial-bit s
log32
- Logarithm 32 bit written in VHDL and implemented in Xilinx
32registergroup
- VHDL MIPS 32位寄存器组的设计-VHDL MIPS 32-bit register set design
ARM32Barrelshifter
- VHDL ARM 32位桶形移位器的设计-VHDL ARM 32-bit barrel shifter design
spanning_tree_vhdl
- 32-bit spanning tree adder in VHDL
mul32
- 32位无符号乘法器 采用VHDL语言编写，很容易改为有符号32位乘法器-32-bit unsigned multiplier using VHDL language, it is easy to signed 32-bit multiplier
lesson6_pipelining
- Analysis of the MIPS 32-bit, pipelined processor using synthesized VHDL
ARM
- ARM32位寄存器的设计，针对于32位寄存器的用VHDL语言编写的代码-ARM32-bit register, designed for 32-bit registers in the language with code written in VHDL
dds32_1
- 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序-Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program
add32
- 32位加法器，基于vhdl语言，主要用于测试算法-32-bit adder, based on the vhdl language, mainly used for testing algorithms
PARALLEL-MULTIPLIER
- vhdl code for a 32 bit parallel multiplier
CORDIC
- 基于VHDL语言的CORDIC算法，长度为32位-CORDIC algorithm based on the VHDL language, length 32-bit
correlator_FPGA_VHDL
- 基于流水线的32位高速数字相关器，ＦＰＧＡ——ＶＨＤＬ——ＥＰ2Ｃ8Ｑ208Ｃ8Ｎ-Based on 32-bit high-speed digital line correlator, FPGA- VHDL- EP2C8Q208C8N